As semiconductor devices become more highly integrated, sizes of individual devices and wires or interconnects become smaller. Also, the distance between devices or wires becomes smaller. Thus, parasitic capacitance between a conductive region and wires increases and impedes normal function of the semiconductor devices. For example, if the parasitic capacitance is increased, resistance capacitance (RC) delay is further created in a signal transfer of a semiconductor device. The RC delay degrades performance characteristics of the semiconductor device and distorts signals being transferred among or within devices. Various approaches have been studied in order to prevent the above problems.
In order to reduce the problems associated with the parasitic capacitance such as the RC delay, there is a method of using a low dielectric layer as a layer which forms structure in a semiconductor device, i.e., an interlayer insulation layer between wires. The low dielectric layer has a low dielectric constant relative to that of a conventional insulation layer used in a semiconductor device. For example, a relative dielectric constant of a silicon nitride layer has a high value of about 8 and that of a silicon oxide layer is 3.7 to 4. The silicon nitride layer is generally used as an etch stopping layer, a capping layer, or a spacer, and the silicon oxide layer is most frequently used as an interlayer insulation layer.
As a material for the low dielectric layer, there are used a layer of organic polymer group and a silicon oxide layer of hydrosilsesquioxane (HSQ) and methylsilsesquoxan (MSQ) formed by a spin on glass (SOG) method, and moreover a silicon oxycarbide layer (SiOC). But, in comparison with a conventional thermal oxide layer and a chemical vapor deposition (CVD) oxide layer, the silicon oxide layer of the SOG group doesn't have a high value of a relative dielectric constant, and it is not easy to finely treat the silicon oxide layer. Thus, there is a problem that it is difficult to form a contact hole or a trench for interconnection by a damascene process because of an inferior etching characteristic. Also, because the curing is not perfect, the silicon oxide layer of the SOG group may absorb water or is polluted in a subsequent step.
The silicon oxycarbide layer may be regarded as the same material with the carbon-doped silicon oxide layer and formed by coating methyl silsesquioxane (MSSQ) by the SOG method or employing a plasma enhanced chemical vapor deposition (PECVD) method by supplying a gas containing silicon and other organic compound of methyl silane group, a source gas containing oxygen atoms from N2O and O2, and a carrier gas selected from N2, NH3, He and Ar. The methyl silane group is formed by substituting a carbon group such as a methyl group (CH3—) for one or more hydrogen of silane (SiH4) gas. The relative dielectric constant of the silicon oxycarbide layer is 2.7 to 2.9, and in case that other variable is constant, it is possible to decrease 25% to 30% of the parasitic capacitance by using the silicon oxycarbide layer instead of the silicon oxide.
There are several drawbacks to using the silicon oxycarbide layer as an interlayer insulation layer. First, with respect to patterning, there is a footing phenomenon of a photoresist pattern formed on the silicon oxycarbide layer. During forming the silicon oxycarbide layer, nitrogen atoms from a source gas or a carrier gas are partially included in the silicon oxycarbide layer. When a photolithography process is performed for patterning the silicon oxycarbide layer, the nitrogen atoms included in the layer are combined with hydrogen ions created when the photoresist is exposed to light, thereby interfering with the reaction that polymer of resin component is formed in the photoresist or with the inverse reaction. As a result, even after developing, the photoresist pattern is not clearly formed and a part of the photoresist remains at the side and bottom of the photoresist pattern like FIG. 1. That is, a footing phenomenon may occur.
The footing phenomenon seriously influences a chemical amplification type photoresist which is frequently being used for forming fine patterns in the formation of a highly integrated semiconductor device. Hydrogen ions are generated by a sensitizer in the photoresist by a sensitization reaction. After sensitization and before development, in a post-exposure bake, the initially generated hydrogen ion induces decomposition or combination reaction of large quantity of polymer related to the resin component in the peripheral photoresist by heat at the chemical amplification type photoresist. In the step, more hydrogen ions can be generated. But, if a small number of the initially generated hydrogen ions are combined with nitrogen included in the silicon oxycarbide layer below the photoresist, although the post-exposure bake is performed, it is impossible to induce a large amount of chemical reaction. Thus, where the photoresist contacts with the silicon oxycarbide layer, the photoresist that should be removed remains even after development because of lack of reaction.
Related to an ashing process, in a step of removing the photoresist pattern used as an etch mask, an ashing process is performed using O2-plasma. At this time, there is a problem that the silicon oxycarbide layer of the interlayer insulation layer is degenerated and damaged by O2-plasma. In case that the silicon oxycarbide layer reacts with the O2-plasma, the relative dielectric constant of the silicon oxycarbide layer is increased up to the similar level with the silicon oxide layer.
In case of the damascene process, the silicon oxycarbide layer is patterned, a trench or a contact hole is filled with a conductive material and then a chemical mechanical polishing (CMP) process is necessarily performed to expose the silicon oxycarbide layer. The characteristic of the silicon oxycarbide layer is mechanically weak so that the phenomena of a micro scratch and lifting frequently occur at the surface of the silicon oxycarbide layer in the CMP process for the damascene process.
Another problem of the silicon oxycarbide layer is a low adhesive force with another layer stacked thereon. Thus, the other layer is not uniformly formed or the stacked layer on the silicon oxycarbide layer is easy to be lifted.
Related to the above problems of the silicon oxycarbide layer, first, a method of eliminating the problem associated with the ashing process can be considered. For example, a hard mask is used and removed together with the photoresist pattern for the low dielectric layer not to be exposed at the O2-plasma for ashing, or the photoresist pattern is removed under the ambient of H2 and N2. The latter method is a forming gas ashing method. But, these methods degrade the process efficiency. Also, the problem of mechanical damage in the CMP process still remains.
Related to the increase in the dielectric constant by ashing and the mechanical damage, it is possible to consider a problem that another insulation layer is thinly stacked on the silicon oxycarbide layer. By using the insulation layer, it is possible to prevent the degeneration and damage of the silicon oxycarbide layer resulting from ashing with the O2-plasma and the direct damage of the silicon oxycarbide layer resulting from the CMP process. But, in case that the silicon oxide layer is stacked on the silicon oxycarbide layer using a silane gas or a tetraethyl orthosilicate (TEOS) gas as a source gas by employing the PECVD method, another problem occurs. That is, the silicon oxycarbide layer has a weak adhesive force with these insulation layers so that these layers are easily lifted in the CMP process.
For more examples related to the adhesive force of the silicon oxycarbide layer, it is possible to consider a case of using a material of an organic polymer group as a layer of a low dielectric constant interlayer insulation layer with the silicon oxycarbide layer. In this case, as the material of the organic polymer group used at a semiconductor device, there are the SiLK and FLARE that are trademarks of the Dow Chemical Company and the Alliedsignal Company, respectively (Refer to “Materials Research Society,” Mat. Res. Soc. Sym. Proc., Vol.476, 1997). The SiLK and FLARE are developed in order to be used as a low dielectric constant interlayer insulation layer. In the event that a material of the organic polymer group is purely used as an interlayer insulation layer and the damascene process is applied, the formed layer has a low thermal characteristic such as a thermal conductivity and an inferior mechanical characteristic. In order to solve this problem, an interlayer insulation layer can be formed of two kinds of layers which are compensative to each other. For example, the interlayer insulation layer of a bottom where a contact hole is formed can be formed of a silicon oxide layer and the interlayer insulation layer of a top where a trench for interconnection is formed can be formed of a layer of the organic polymer group. However, the layer of the organic polymer group is formed by employing a coating method such as that disclosed in IEEE 2000, “Copper Dual Damascene Interconnects with Very Low-k Dielectrics Targeting for 130 nm Node.”
At this time, if the silicon oxycarbide layer can be used as the interlayer insulation layer of the bottom, it will be desirable. But, in this case, the silicon oxycarbide layer has a low adhesive force so that the coated organic polymer layer is not uniformly formed and a process failure is induced. Particularly, there is a problem that a coating layer is easily lifted or thickness of the coating layer is not uniform at the peripheral part of a wafer.